1. Field of the Invention
This invention relates to the field of electronic devices, and in particular to voltage generators for memory devices.
2. Description of Related Art
The reliability, or longevity, of a semiconductor memory device has been found to be related to the stress imposed on the device by rapid voltage transitions, particularly rapid high voltage transitions used to write or erase the memory contents.
Electrically erasable (EE) memory devices are particularly well suited for techniques that control the application of stress-inducing voltage transitions in order to improve the longevity of the device. Typically, EE devices are used as programmable read-only memories, wherein the EE device is relatively infrequently programmed to contain a data set that is frequently read. Because the programming is relatively infrequent, the speed at which the programming occurs is not as critical as other parameters of the design, and in particular, less critical than the longevity of the device.
FIG. 1 illustrates an example voltage generator 100 commonly used for programming and erasing an electrically erasable memory device. The generator 100 is designed to provide an output voltage 165 that increases from zero volts to a high voltage reference voltage at a controlled rate. The value of the high voltage reference, typically in the 10 to 12 volt range, is determined by fabricating and testing samples of the device to determine an optimal value, based on process parameters and other factors. A reference voltage Vref 115 is provided for controlling the peak value of the output voltage 165, typically from a band-gap voltage source, common in the art. The controller 190 effects a charge transfer from the source of the reference voltage 115 to a comparator 150, via switches S1110 and S2120, and capacitors C1130 and C2140, using techniques common in the art. The controller 190 asserts switch control Sa 101 to effect a charging of capacitor C1130 to the reference voltage 115, while de-asserting switch control Sb 102 to isolate capacitor C1130 from C2140. Thereafter, the controller 190 de-asserts switch control Sa 101 and asserts switch control Sb 102, thereby isolating capacitor C1130 from the reference voltage Vref 115, and coupling the capacitors C1130 and C2140 together. If the voltage of capacitor C2140 at the time of coupling to capacitor C1130 is less than the voltage on the capacitor C1130 (which, at the time of coupling, is equal to the reference voltage 115), capacitor C1130 transfers charge to capacitor C2140, thereby raising the voltage level of capacitor C2140. The ratio of the capacitance of capacitor C1130 and capacitor C2140, and the difference in voltage between the capacitors 130, 140 at the time of coupling, determine the amount of the voltage increase at each coupling. Using this charge transfer technique, common in the art, the voltage Vramp 145 on the capacitor C2140 increases asymptotically to the voltage reference 115, the rate of increase being determined by the ratio of the capacitance of the capacitors 130, 140.
A voltage controlled high-voltage source 160 provides the high-voltage output 165. The control voltage 155 that controls the high-voltage source 160 is provided by a closed-loop feedback system comprising a scaler 170 and the comparator 150. The scaler 170 scales the high-voltage output 165 by a factor S, and this scaled voltage 175 is compared to the aforementioned voltage Vramp 145. The feedback control signal 155 controls the high-voltage output 165 to track the Vramp 145 signal, at the scale factor S. That is, if the scale factor S is 5/8, the high-voltage output 165 is 8/5*Vramp 145. Because Vramp 145 increases to Vref 115, the high-voltage output 165 increases to 8/5*Vref 115. After providing the increasing high-voltage output 165 to the device that utilizes this voltage source, such as an EE memory device, the controller 190 closes switch S0180 to deplete the charge on capacitor C2 and reduce its voltage to zero, thereby reducing the output voltage 165 to zero. The above process is repeated as required, whenever the increasing output voltage 165 is required.
As mentioned above, the peak of the high-voltage output 165 is preferably trimmed to optimize the longevity of the device that receives this high-voltage output 165. This trim is effected by modifying the scale factor S, typically by physically modifying the devices that form the scaler 170. For example, a conventional scaler 170 is a capacitor divider circuit, and the trimming of the scaler is effected by increasing or decreasing the plate area of one or more of the capacitors forming the scaler 170. This typically requires a change to at least one of the metal masks used to fabricate the device, and cannot be economically applied to customize the high-voltage output 165 of individual voltage generators 100.
It is an object of this invention to provide a high-voltage generator that can be trimmed without a mask change. It is a further object of this invention to provide a voltage generator that can be individually trimmed after fabrication. It is a further object of this invention to provide a high-voltage generator that can be optimized for writing and erasing electrically erasable programmable devices.
These objects, and others, are achieved by providing a programmable reference voltage that is used for controlling a high-voltage source. A programmable voltage divider is used to scale a fixed reference voltage to a scaled reference value that is used to control the generation of a high voltage source. A comparator provides a feedback signal that is based on a difference between the scaled reference voltage and a scaled output voltage. This feedback signal controls the voltage-controlled output voltage source, so as to track the scaled reference value. In a preferred embodiment, the scale factor associated with the output voltage remains constant, whereas the scale factor associated with the reference voltage is programmable. In alternative embodiments of this invention, the reference scaling factor defaults to a mid-range value, and a bias offset is provided to easily select an output voltage value for either programming or erasing the contents of a programmable memory device.